This is a pseudo-mirror of www.bores.com DSP intro at http://www.bores.com/courses/intro/chips/6_56002.htm [sic] as per the policy of this site.
This mirror was created from the source on 03/08/2000 at 22:46 Central Time.
Commercial information, time-dependent information, and all the damn JAVA scripts have been removed. All "htm" extensions have been changed to the proper "html" extensions. Has also been edited for
coherence, proper-linkage, and better document flow.
Copied without permission.
The problem of fixed point processors is quantisation error, caused by the limited fixed point precision. Motorola reduce this problem in the DSP56002 by using a 24 bit integer word length:
They also use three internal buses - one for program, two for data (two operands). This is an extension of the standard Harvard architecture which goes beyond the usual trick of simply adding a cache, to allow access to two operands and the instruction at the same time.
Of course, the problem of 24 bit fixed point is its expense: which probably explains why Motorola later produced the cheap, 16 bit DSP56156 - although this looks like a 16 bit variant of the DSP56002:
And of course there has to be a floating point variant - the DSP96002 looks like a floating point version of the DSP56002:
The DSP96002 supports multiprocessing with an additional 'global bus' which can connect to other DSP96002 processors: it also has a new DMA controller with its own bus
| Last updated: 9th January 1997 | http://www.bores.com/courses/intro/chips/6_56002.htm